1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a highly conductive silicide across the source/drain regions of a transistor using a one-step anneal. The source/drain regions of the transistor are advantageously formed by etching through a single ("unitary") implant area.
2. Description of the Related Art
Active electronic devices are well known in the art. They are classified as any device which is not passive. A transistor is but one example of an active device. Therefore, a transistor is regarded as a basic building block of an integrated circuit containing numerous, interconnected active devices.
Transistor fabrication typically involves forming a gate conductor spaced from a single crystalline silicon substrate by a gate dielectric. Source/drain impurity regions (hereinafter "junctions") are then formed within the substrate, using the gate conductor as an implant mask, according to the well known self-aligned process. The gate conductor therefore ends up interposed between a pair of junctions, all of which are formed exclusively within active areas of the substrate.
Isolation structures are used to isolate the junctions of a transistor from other active areas spaced throughout the substrate. Isolation structures may comprise shallow trenches etched in the substrate that are filled with a dielectric using, e.g., chemical vapor deposition. Alternately, isolation structures may comprise local oxidation of silicon ("LOCOS") structures which are thermally grown using, e.g., wet oxidation.
Ion implantation of dopants is primarily used to form junctions. Alternatively, although less often used, junctions may be formed by diffusion doping. Ion implantation involves placing energetic, charged atoms or molecules directly into the substrate surface. The resulting junctions self-align between the isolation structures and, if used, oxide spacers arranged on opposing sidewall surfaces of the gate conductor. The number of implanted dopant atoms entering the substrate is more easily controlled using ion implantation. Ion implantation results injunctions having a majority carrier opposite that of the surrounding bulk substrate or well area.
In order to form highly conductive ohmic contacts in connecting regions (i.e., "windows") between transistor junctions and overlying interconnect, it is oftentimes necessary to incorporate a layer of refractory metal at the juncture. The refractory metal, when subjected to high enough temperature, reacts with the silicon substrate in the contact window to form what is commonly called a "silicide". Any unreacted metal is removed after formation of the silicide. Silicides are well known in the art and provide dependable silicon contact as well as low ohmic resistance.
Self-aligned silicides on source/drain junctions, i.e., "salicides", have increased in popularity due to the shrinking dimensions of conventional transistors. As the contact window decreases in size, it is important that contact resistance remain relatively low. Further, aligning contact windows via a separate masking step makes minimizing source/drain junctions difficult. For these reasons, salicides have become a mainstay in semiconductor processing due to their ease of application--i.e., their self-aligned application. When a metal is deposited and heated on a semiconductor topography, the silicide reaction occurs wherever the metal is in contact with a region heavily concentrated with silicon. For example, silicide contacts may be formed simultaneously over junctions of a silicon-based substrate and over a polycrystalline silicon ("polysilicon") gate. However, as device dimensions shrink, so does the spacing between contact windows. Thus, lateral, silicide migration between closely spaced contact windows must be carefully monitored and controlled. Otherwise, a phenomenon often referred to as silicide shorting or "bridging" can occur.
Bridging often arises when a silicide, such as titanium silicide is allowed to form between silicon contact windows, such as between a polysilicon gate and junctions arranged within a silicon-based substrate. In a lightly doped drain (LDD) process, sidewall spacers normally exist on lateral surfaces of the gate conductor so that heavily concentrated source/drain junctions may be formed which are spaced from the gate. The sidewall spacers are relatively small in size. They are typically composed of silicon dioxide or silicon nitride. During the anneal stage of titanium silicide formation, the semiconductor topography undergoes temperature cycling in an inert-gas. Silicon atoms within the spacers may diffuse into regions of the titanium arranged upon the spacers, or vice versa. The silicon and the titanium may react over or within the spacer regions, causing titanium silicide to undesirably form. Unfortunately, the presence of titanium silicide at the spacers provides a capacitive-coupled or fully conductive path between the polysilicon gate conductor and the source/drain junctions.
Titanium silicide shorting can, in some instances, be prevented if the anneal cycle is carefully controlled. Many researchers advocate a multiple step salicide forming process. First, a refractory metal such as titanium is deposited over the entire wafer. Next, the metal film is heated to a low temperature in the presence of a nitrogen ambient in order to form a reacted, relatively high-resistance silicide in the contact windows. The low temperature nature of this anneal step helps inhibit cross-diffusion between silicon atoms within a spacer and titanium atoms of the metal layer. After the first anneal, the unreacted metal is removed using a wet chemical etch (e.g., NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O), thereby leaving reacted metal or metal silicide in the contact windows. Finally, a higher temperature anneal is performed in order to produce a lower resistivity silicide.
Two anneal steps are typically used to prevent unwanted or excessive silicide formation in regions where silicide is undesired, e.g., in the gate sidewall spacer which bears only a relatively low concentration of silicon. Additionally, it is important that the anneal steps promote silicide formation in regions where silicon concentration is relatively high, e.g., upon the conductor and the source/drain junctions. If the first anneal temperature is comparable to the second (higher) anneal temperature, then silicon dioxide layers could be consumed by the formation of silicide. Thus, the first anneal must be maintained at a maximum temperature of approximately 600-700.degree. C., while the subsequent anneal may extend well above 850.degree. C.
This two step anneal process has its share of problems. First, the silicon substrate is removed from the annealing chamber after the first anneal to etch the remaining metal therefrom. The withdrawal of the substrate from the chamber allows native oxides or other impurities to grow or deposit upon the reacted metal silicide. Such impurities may increase contact resistance in the contact window. Further, if the first anneal temperature exceeds a pre-determined level, unwanted salicidation may occur on spacers adjacent to the sidewalls of the gate conductor. Unfortunately, when the contact window contains a heavily doped source/drain junction, it is often necessary to increase the first anneal temperature given the relative absence of silicon with respect to impurity atoms.
It is therefore desirable that a semiconductor fabrication process be developed in which highly conductive silicide contacts are formed that exhibit no silicide shorting. Thus, it is important to heat the refractory metal within the contact window to a relatively high temperature so that silicide formation therein is promoted. However, it is also critical that the interaction of silicon atoms with metal atoms during high temperature anneal is avoided in areas where silicide formation is undesired. Yet further, a process is needed whereby the contact area is not exposed to atmospheric conditions during the formation of a silicide that exhibits low resistivity. Preventing the exposure of the silicide to ambient oxide is necessary to ensure good ohmic contact at contact windows of the transistor.